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integrated silicon solution, inc. 1 re v . b 08/11/2010 72 mb (2m x 36 & 4m x 18) q u adp (bur st of 4) sync hr onous srams august 2010 i 7 q fe atures ? 2 m x 36 or 4 m x 1 8 . o n- ch ip del ay - l oc ke d l oop ( d ll) f or wi de d ata v a li d wi ndo w . s e par at e r ead an d wr i te p or ts wi th c onc ur r ent r ead and wr ite op er ati ons. s y nc hr on ous pi pel in e r ea d wi th l ate wr ite ope r a- tio n . d ou b l e da ta r a te (ddr) inte r f ace f o r rea d an d wr it e i nput por t s . f ix e d 4- bi t b ur s t f or r e ad and wr ite ope r ati ons. c lo c k s t o p s upp or t. t w o i n p u t c l o c ks ( k a nd k ) f o r a d d re s s a n d co n - tr ol r e gis t e r ing at r i s i ng edg es onl y . t w o e c ho c l o c k s ( c q a nd c q ) th at a r e d e l i v e r e d si m u lta neo us ly wit h da ta. + 1 .8v c or e po wer s uppl y and 1.5 , 1.8 v v ddq , us ed w i th 0.75 , 0. 9v v re f . h st l in put and outp ut l e v el s . r egi s ter ed add r e ss es, wr i te an d r ea d c ontr ol s , b y te wr ite s , d ata in, and dat a ou tpu ts . f ull da ta c oh er enc y . b o und ar y s c a n us i ng l i m i te d s et o f j t a g 114 9.1 fun c ti ons. by t e w r ite ca pab il ity . f ine ba ll g r i d ar r a y ( f b g a) pa c k a g e - 15m m x 17 mm bod y s i ze - 1mm pi tc h - 165 - b al l ( 1 1 x 1 5 ) ar r a y p r ogr amm ab l e im ped anc e o utpu t dr i v e r s v i a 5x us er - s up pl ied pr ec is io n r e s i s t o r . de sc ri pt i o n t he 72 mb is61qdpb4 2 m36 a nd is61qdpb4 4 m18 a r e s y n c h r o n ou s , h i g h - p e r fo r - man c e cmo s s tati c r a ndom ac c es s m emo r y ( s ra m) dev i c e s . t h es e sr ams ha ve se par ate i/o s , el imi na tin g the n eed for hi gh- s peed bus tur na r o und . t he r i si ng edg e of k c l o c k i nit iat e s the r e ad/w r i te ope r a tio n , a nd a l l in ter nal op er ati ons ar e se lf- t i m ed . refe r to th e t i min g re fer enc e diag r am f or t r u th t ab l e o n p age 8 f or a de s c r i pt i on of t h e b a s i c o p e r a- ti o ns of t he s e quadp (burst of 4) s r a m s. rea d an d wr it e ad dr es se s a r e r egi st er ed o n al ter - nat ing r i si ng e dge s of t he k c l o c k . re ads and w r i t es ar e p er for me d i n do ubl e d ata r a te. t h e fol l o w in g a r e r egi ste r e d i nte r n all y on t he r i si ng e dge of t he k c lo ck: r ea d/wr i te a ddr es s r ea d en ab le w r i te enab l e b y t e wr ite s f o r b u r s t ad dr es se s 1 and 3 d ata - i n f or b ur s t ad dr es ses 1 and 3 t he f oll owi ng ar e r egi s ter ed on t he r i si ng e dge of the k clo ck : b y t e wr ite s f o r b u r s t ad dr es se s 2 and 4 d ata - i n f or b ur s t add r ess es 2 and 4 by te wr ite s c an c han ge w i th the c or r e s p ondi ng dat a- in t o ena ble or dis ab l e wr i t es on a p e r - b y te bas is . a n in ter nal wr it e bu ffer en abl es the da ta- i n s to be r e gi s- ter ed one cy c l e afte r the w r i te a ddr es s . t he fir s t dat a- in bu r s t is c l o c k ed on e cy c l e la ter t han the wr i t e co mma nd si gna l, a nd t he s e c o n d bu r s t i s tim ed to the fol l ow ing r i s i ng ed ge o f the k cl oc k. t w o fu ll cl oc k cy c l es ar e r e qui r ed to c omp let e a w r i te o per a- tio n . t he d ev i c e i s oper a ted w i th a s i n gle + 1.8v po wer su ppl y and is c omp ati ble wit h hs t l i/o i n te r f ac es. .
2 integrated silicon solution, inc. rev. b 08/112010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams x36 fbga pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq nc /sa * sa w bw 2 k bw 1 r sa nc/sa* cq b q27 q18 d18 sa bw 3 k bw 0 sa d17 q17 q8 c d27 q28 d1 9 v ss sa nc sa v ss d1 6 q7 d8 d d28 d2 0 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d2 9 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d1 4 q14 q5 g d30 d2 2 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d1 2 q4 d4 k q32 d3 2 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d1 1 q11 q2 m d3 3 q34 d25 v ss v ss v ss v ss v ss d1 0 q1 d2 n d34 d2 6 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d3 5 q26 sa s a sa sa q9 d0 q0 r tdo tck sa sa sa sa sa sa tms tdi no te: * t he f ollowing pins are res erved for higher densit ies: 10a for 144 mb, and 2a f or 288m b. qvld pin (6p) is not supported. x18 fbga pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 a cq nc /sa* sa w bw 1 k nc r sa sa cq b nc q9 d9 sa nc k bw 0 sa nc nc q8 c nc nc d1 0 v ss sa nc sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d1 3 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d1 4 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d1 6 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa s a sa sa nc d0 q0 r tdo tck sa sa sa sa sa sa tms tdi no te: * t he f ollowing pins are res erved for higher densit ies: 2a for 144 mb. qvld pin (6p) is not supported. nc nc nc nc
integrated silicon solution, inc. 3 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams pin description symbol pin number description k, k 6b, 6a input clock. . cq, cq 11a, 1a output echo clock. doff 1h dll disable when low. sa 3a, 9a, 4b, 8b, 5c, 7c, 5n, 6n, 7n, 4p, 5p, 7p, 8p, 3r, 4r, 5r, 7r, 8r, 9r 2 m x 36 address inputs. sa 3a, 9a, 10 a, 4b, 8b, 5c, 7c, 5n, 6n, 7n, 4p, 5p, 7p, 8p, 3r, 4r, 5r, 7r, 8r, 9r 4 m x 18 address inputs. d0 ? d8 d9 ? d17 d18 ? d26 d27 ? d35 10p, 11n, 11m, 10k, 11j, 11g, 10e, 11d, 11c 10n, 9m, 9l, 9j, 10g, 9f, 10d, 9c, 9b 3b, 3c, 2d, 3f, 2g, 3j, 3l, 3m, 2n 1c, 1d, 2e, 1g, 1j, 2k, 1m, 1n, 2p 2 m x 36 data inputs. q0 ? q8 q9 ? q17 q18 ? q26 q27 ? q35 11p, 10m, 11l, 11k, 10j, 11f, 11e, 10c, 11b 9p, 9n, 10l, 9k, 9g, 10f, 9e, 9d, 10b 2b, 3d, 3e, 2f, 3g, 3k, 2l, 3n, 3p 1b, 2c, 1e, 1f, 2j, 1k, 1l, 2m, 1p 2 m x 36 data outputs. d0 ? d8 d9 ? d17 10p, 11n, 11m, 10k, 11j, 11g, 10e, 11d, 11c 3b, 3c, 2d, 3f, 2g, 3j, 3l, 3m, 2n 4 m x 18 data inputs. q0 ? q8 q9 ? q17 11p, 10m, 11l, 11k, 10j, 11f, 11e, 10c, 11b 2b, 3d, 3e, 2f, 3g, 3k, 2l, 3n, 3p 4 m x 18 data outputs. w 4a write control, active low. r 8a read control, active low. bw 0, bw 1, bw 2, bw 3 7b, 7a, 5a,5b 2 m x 36 byte write control, active low. bw 0, bw 1 7b, 5a 4 m x 18 byte write control, active low. v ref 2h, 10h input reference level. v dd 5f, 7f, 5g, 7g, 5h, 7h, 5j, 7j, 5k, 7k power supply. v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply. v ss 4c, 8c, 4d, 5d, 6d, 7d, 8d, 5e, 6e, 7e, 6f, 6g, 6h, 6j, 6k, 5l, 6l, 7l, 4m, 5m, 6m, 7m, 8m, 4n, 8n ground . zq 11h output driver impedance control. tms, tdi, tck 10r, 11r, 2r ieee 1149.1 test inputs (1.8v lvttl lev- els). tdo 1r ieee 1149.1 test output (1.8v lvttl level). nc for x36 nc for x18 2a, 10a, 6c, 6p, 6r 2a, 7a, 1b, 5b, 9b, 10b, 1c, 2c, 6c, 9c, 1d, 9d, 10d, 1e, 2e, 9e, 1f, 9f, 10f, 1g, 9g, 10g, 1j, 2j, 9j, 1k, 2k, 9k, 1l, 9l, 10l, 1m, 2m, 9m, 1n, 9n, 10n, 1p, 2p, 6p, 9p, 6r
4 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q sram features read operations the sram operates continuously in a burst-of-four mode. read cycles are started by registering r in active low state at the rising edge of the k clock. r can be activated every other cycle because two full cycles are required to complete the burst of four in ddr mode. a set of free-running echo clocks, cq and cq, are produced internally with timings identical to the data-outs. the echo clocks can be used as data capture clocks by the receiver device. t he data corresponding to the first address is clocked 2 .5 cycles later by the rising edge of the k clock. the data corresponding to the second burst is clocked 3 cycles later by the following rising edge of the k clock. the third data-out is clocked by the subsequent rising edge of the k clock, and the fourth data-out is clocked by the subsequent rising edge of the k clock. a nop operation (r is high) does not terminate the previous read. write operations write operations can also be initiated at every other rising edge of the k clock whenever w is low. the write address is provided simultaneously. again, the write always occurs in bursts of four. the write data is provided in a ? late write ? mode; that is, the data-in corresponding to the first address of the burst, is presented 1 cycle later or at the rising edge of the following k clock. the data-in corresponding to the second write burst address follows next, registered by the rising edge of k . the third data-in is clocked by the subsequent rising edge of the k clock, and the fourth data-in is clocked by the subsequent rising edge of the k clock. block diagram 2 m x 36 ( 4 m x 18) mem or y array wr it e/read decode s ense am ps wr it e dr iv er select o utput control data reg ad d reg cont ro l logi c cloc k ge n output reg ou tp ut select out put dr iv er 72 (o r 36 ) 72 (o r 36 ) 144 (or 72 ) 36 ( or 18) q (d at a- out) cq, cq (ech o cloc k out ) d (data-in) 36 (o r 18 ) addres s r w bw x k k c doff 4 (or 2) 19 (o r 20 ) 19 (or 20 ) 72 (or 36 ) 72 (or 36 )
integrated silicon solution, inc. 5 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q the data-in provided for writing is initially kept in write buffers. the information in these buffers is written into the array on the third write cycle. a read cycle to the last two write addresses produces data from the write buffers. the sram maintains data coherency. during a write, the byte writes independently control which byte of any of the four burst addresses is written (see x18/x36 write truth tables on pages 10 - 11 and ti ming ref ere nce di agram for truth table o n pa ge 8 ). whenever a write is disabled (w is high at the rising edge of k), data is not written into the memory. rq programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. for example, an rq of 250 ? results in a driver impedance of 50 ? . the allowable range of rq to guarantee impedance matching is between 175 ? and 350 ? , with the tolerance described in programmable impedance output driver dc electrical characteristics on page 16. the rq resistor should be placed less than two inches away from the zq ball on the sram module. the capacitance of the loaded z q tr ace must be less than 3 pf. the zq pin can also be directly connected to v ddq to obtain a minimum impedance setting. zq must never be connected to v ss . programmable impedance and power-up requirements periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. at power-up, the driver impedance is in the middle of allowable impedances values. the final impedance value is achieved within 2048 clock cycles. depth expansion separate input and output ports enable easy depth expansion, as eac h port can be selected and deselected independently. read and write operations can occur simultaneously without affecting each other. also, all pending read and write transactions are always completed prior to deselecting the corresponding port.
6 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams applicati on e xa mple sa r w bw 0 bw 1 k k d q zq sram #4 r =2 50 ? vt data in data out ad dr ess r w bw mem ory controller s ou rce clk s ou rce clk sa r w bw 0 bw 1 k k d q zq sram #1 r=250 ? vt vt r r =50 ? vt=v ref r sram1 inp ut cq sram1 inp ut cq sram4 inp ut cq sram4 inp ut cq cq cq cq cq power-up and power-down sequences the following sequence is used for power-up: 1. the power supply inputs must be applied in the following order while keeping doff in low logic state: 1) vdd 2) vddq 3) vref 2. start applying stable clock inputs (k, k, c, and c). 3. after clock signals have stabilized, change doff to high logic state. 4. once the doff is switched to high logic state, wait an additional 1024 clock cycles to lock the dll. notes: 1. the power-down sequence must be done in reverse of the power-up sequence. 2. vddq can be allowed to exceed vdd by no more than 0.6v. 3. vref can be applied concurrently with vddq.
integrated silicon solution, inc. 7 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q the timing referenc e d i ag ram for truth t able on page 8 is helpful i n understanding th e clock and w ri t e tru th tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. all read and write commands are issued at the beginning of cycle ? t? . state diagram power-up write nop load new write address ddr-ii write read nop load new read address read write read write read write read write notes: 1. internal burst counter is fixed as four-bit linear; that is, when first address is a0+0, next internal burst addresses are 2. read refers to read active status with r = low. read refers to read inactive status with r = high. 5. state machine control timing sequence is controlled by k. 4. the read and write state machines can be active simultaneously. 3. write refers to write active status with w = low. write refers to write inactive status with w = high. increment read address increment write address ddr-ii read always always d count = 2 d count = 0 d count = 0 d count = d count + 1 d count = d count + 1 d count = 2 d count = 2 d count = 2 always always write d count = 1 read d count = 1 . a0+1, a0+2, and a0+3
8 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad (burst of 4) synchronous srams timing reference diagram fo r truth table t t+1 t+2 t+3 t+4 r ea d a write b b a db db+1 db+2 db+3 k c lock k cl ock r w bw x a ddre ss data-in da ta-out cq cl ock cq cl ock cycle qa qa+1 qa+2 qa+3
integrated silicon solution, inc. 9 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q clock truth table (use the following table with the timing reference diagram for truth table .) mode clock controls data in data out kr w d b d b+1 d b+2 d b+3 q a q a+1 q a+2 q a+3 stop clock stop x x p revious state p revious state prev ious state prev ious state p revious state pre vious state p revious state prev ious state no operation (nop) l h h h x x x x high-z high-z high-z high-z read b l h lxxxxx dout at k (t + 2.5) dout at k (t + 3.0 ) dout at k (t + 3 .5) dout at k (t + 4.0 ) write a l h xl din at k (t + 1) din at k (t + 1.5) din at k (t + 2) din at k (t + 2.5) xxxx notes : 1. internal burst counter is always fixed as four-bit. 2. x = ? don? t care ? ; h = logic ? 1 ? ; l = logic ? 0 ? . 3. a read operation is started when control signal r is active low 4. a write operation is started when control signal w is active low. before entering into stop clock, all pending read and write com- mands must be completed. 5. consecutive read or write operations can be started only at every other k clock rising edge. if two read or write operations are issued in consecutive k clock rising edges, the second one will be ignored. 6. if both r and w are active low after a nop operation, the write operation will be ignored. 7. f or timing defin itions, refer to the a c characte r isti c s on page 17. signals must ha ve ac specifications at timings indicated in parenthesis with respect to switching clocks k and k.
10 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q x36 write truth table use the following table with the timing reference diagram for truth table on page 8. operation k (t+1) k (t+1.5) k (t+2 )k (t+2.5) bw 0 bw 1 bw 2 bw 3 d b d b+1 d b+2 d b+3 write byte 0 l h l h h h d0-8 (t+1) write byte 1 l h h l h h d9-17 (t+1) write byte 2 l h h h l h d18-26 (t+1) write byte 3 l h h h h l d27-35 (t+1) write all bytes l h l l l l d0-35 (t+1 ) abort write l h hhhhdon ? t care wri te byte 0 l h l h h h d0-8 (t+1.5) write byte 1 l h h l h h d9-17 (t+1.5) write byte 2 l hh h l h d18-26 (t+1.5) write byte 3 l h hhhl d27-35 (t+1.5) write all bytes l h l l l l d0-35 (t+1.5 ) abort write l h hhhh don ? t care w rite byte 0 l h l h h h d0-8 (t+2) write byte 1 l h h l h h d9-17 (t+2) write byte 2 l hhhlh d18-26 (t+2) write byte 3 l h hhhl d27-35 (t+2) write all bytes l h l l l l d0-35 (t+2 ) abort write l h hhhh don ? t care wri te byte 0 l h lh hh d0-8 (t+2.5) write byte 1 l h h l h h d9-17 (t+2.5) write byte 2 l h h h l h d18-26 (t+2.5) write byte 3 l hhhhl d27-35 (t+2.5) write all bytes l h l l l l d0-35 (t+2.5 ) abort write l hhhhh don ? t care notes ; 1. for all cases, w needs to be active low during the rising edge of k occurring at time t. 2. f or t iming definitions refer to the ac chara cteristics on page 17. s ignals must have ac specifications with re s pect to switching clocks k and k.
integrated silicon solution, inc. 11 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i ? 3 q x18 write truth table use the following table with the timing reference diagram for truth table on page 8. operation k (t+1) k (t+1.5) k (t+2 )k (t+2.5) bw 0 bw 1 d b d b+1 d b+2 d b+3 write byte 0 l h l h d0-8 (t+1) write byte 1 l h h l d9-17 (t+1) write all bytes l h l l d0-17 (t+1 ) abort write l h hh don ? t care wri te byte 0 l h l h d0-8 (t+1.5) write byte 1 l h h l d9-17 (t+1.5) write all bytes l h l l d0-17 (t+1.5 ) abort write l h hh don ? t care w rite byte 0 l h l h d0-8 (t+2) write byte 1 l h h l d9-17 (t+2) write all bytes l h l l d0-17 (t+2 ) abort write l h hh don ? t care wri te byte 0 l h l h d0-8 (t+2.5) write byte 1 l h h l d9-17 (t+2.5) write all bytes l h l l d0-17 (t+2.5 ) abort write l h hh don ? t care notes ; 1. for all cases. w needs to be active low during the rising edge of k occurring at time t. 2. f or t iming definitions refer to the ac chara cteristics on page 17. signals must have ac specificat ions with re spect to s wit ching clocks k and k.
12 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q absolute maximum ratings item symbol rating units power supply voltage v dd -0.5 to 2.9v v output power supply voltage v ddq -0.5 to 2.9v v input voltage v in -0.5 to vdd+0.3v v data out voltage v dout -0.5 to 2.6 v operating temperature t a 0 to 70 c junction temperature t j 110 c storage temperature t stg -55 to +125 c note: stresses greater than those listed in this table can cause permanent damage to the device. this is a stress rating only and fun c- tional operation of the device at these or any other conditions above those indicated in the operational sections of this datas heet is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
integrated silicon solution, inc. 13 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams re comm ended dc oper ating conditions (t a = 0 to + 70 c) pa rameter sym bol minimu m t ypica l ma ximu m u nits notes s upply volt age v dd 1.8 - 5% 1.8 + 5% v 1 o utpu t drive r su pply volt age v ddq 1.4 1.9 v 1 input high volt age v ih v ref +0.1 v ddq + 0.2 v 1, 2 input low volt age v il -0 .2 v ref - 0.1 v 1, 3 input referen ce voltage v ref 0.68 0.95 v 1, 5 cloc ks signal v olt age v in - clk -0 .2 v ddq + 0.2 v 1, 4 1. all voltages are ref ere nced to v ss . all v dd , v ddq , and v ss pins mu st be conn ect ed. 2. v ih (m ax) ac = s ee 0v ers hoo t and undersho ot timi ngs . 3. v il (m in) ac = s ee 0v ersho ot and unde rshoot t imings . 4. v in-clk specif ie s the ma ximum allowable dc ex curs ions of ea ch clock ( k and k ). 5. p eak-to-peak ac com ponent su per impos ed on v ref may no t e xce ed 5% of v re f. 0vershoot and undershoot timings pbga therma l char acter is tics item symbol rating uni ts t her mal re sis tan ce jun cti on to ambient (airflow = 1m/s) r ja 18.6 c/w t her mal re sis tan ce jun cti on to case r jc 4.3 c/w t her mal re sis tan ce jun cti on to pins r jb 1.77 c/w v ddq 20 % min cycle time v ddq +0.6v gnd -0.6v gnd 20% min cycle time overs hoo t tim ing u nd ers hoo t ti ming v ih (max) ac v il (m in) ac
14 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams capa cita nce (t a = 0 to + 70 c, v dd = 1.8v -5%, +5 %, f = 1mhz) p ara meter symbol test condit io n maxi mu m u ni ts input capacitance c in v in = 0v 4 pf data -in c apa citanc e (d 0? d3 5) c din v din = 0v 4 pf dat a-out ca paci tan ce (q0?q 35) c c out v out = 0v 4 pf cloc ks cap acita nce (k , k ) clk v clk = 0v 4 pf dc electri cal c haract er ist ic s (t a = 0 to + 70 c, v dd = 1.8v -5 %, +5%) parameter sym bo l minimum maximum unit s no tes x36 av era ge po wer supply ope rat ing curr ent (i out = 0, v in = v ih or v il ) i dd 33 i dd 30 i dd 27 i dd 25 i dd 33 i dd 30 i dd 27 i dd 25 ? 950 1050 850 750 900 1000 800 700 m a 1 x18 aver age po wer su pply ope rat ing cu rrent (i out = 0, v in = v ih or v il ) ? m a 1 p owe r s upp ly stan dby c urr ent (r = v ih , w = v ih . all other inputs = v ih or v ih , i ih = 0) i sb ? 4 00 ma 1 input l ea kage curr en t, any i nput ( exc ept jtag) (v in = v ss or v dd ) i li -2 +2 a o ut put leaka ge c urr ent (v out = v ss or v ddq , q in h igh-z) i lo - 2 + 2 a o utp ut ? hi gh? le vel v olt age (i oh = -6ma) v oh v ddq -.4 v ddq v 2, 3 output ? lo w? le vel v olt age (i ol = +6ma) v ol v ss v ss +.4 v 2, 3 jtag le akage cu rre nt (v in = v ss or v dd ) i lijtag - 100 + 100 a 4 1. i out = c hi p o ut put c urr en t. 2. minimum impe dance o utp ut driver. 3. 4. for jtag inpu ts o nly. jedec stand ard j esd8 -6 cla ss 1 c omp at ib le.
integrated silicon solution, inc. 15 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q typical ac input characteristics item symbol minimum maximum notes ac input logic high v ih (ac) v ref + 0. 2 1, 2, 3, 4 ac input logic low v il (ac) v ref - 0. 2 1, 2, 3, 4 clock input logic high (k, k , c, c) v ih-clk (ac) v ref + 0. 2 1, 2, 3 clock input logic low (k, k , c, c) v il-clk (ac) v ref - 0. 2 1, 2, 3 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. performance is a function of v ih and v il levels to clock inputs. 3. see the ac input definition diagram. 4. see the ac input definition diagram. the signals should swing monotonically with no steps rail-to-rail with input signals never ring- ing back past vih (ac) and vil (ac) during the input setup and input hold window. vih (ac) and vil (ac) are used for timing pur - poses only. ac input definition programmable impedance output driver dc electrical characteristics (t a = 0 to +70 c, v dd = 1.8v -5%, +5%, v ddq = 1.5, 1.8v) parameter symbol minimum maximum units notes output ? high? level voltage v oh v ddq / 2 v ddq v1, 3 output ? low ? level voltage v ol v ss v ddq / 2 v 2, 3 1. i oh = 15% @ v oh = v ddq / 2 for: 175 ? rq 350 ? . 2. i ol = 15% @ v ol = v ddq / 2 for: 175 ? rq 350 ? . 3. parameter tested with rq = 250 ? and v ddq = 1.5v. v ih (ac) v ref v il (ac) setup time hold time v ref k k v rail v -rail vddq 2 ------------------ ?? ?? rq 5 -------- ? ? ? ? ? vddq 2 ------------------ ?? ?? rq 5 -------- ? ? ? ? ?
16 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q ac test conditions (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%, v ddq = 1.5, 1.8v) parameter symbol conditions units notes output driver supply voltage v ddq 1.5, 1.8 v input high level v ih v ref +0.5 v input low level v il v ref -0.5 v input reference voltage v ref 0.75, 0.9 v input rise time t r 0.35 ns input fall time t f 0.35 ns output timing reference level v ref v clocks reference level v ref v output load conditions 1, 2 1. see ac test loading . 2. parameter tested with rq = 250 ? and v ddq = 1.5v. ac test loading q 50 ? 50 ? 5pf 0.75, 0.9v 0.75, 0.9v test comparator
integrated silicon solution, inc. 17 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams ac characteristics (vdd = 1.8v 0.1v, ta=0 c to +70 c) parameter 25 (400 mhz) 27 (375 mhz) 30 (333 mhz) 33 (300 mhz) unit notes min max min max min max min max clock clock cycle time (k, k) tkhkh 2.50 7.5 2.66 7.5 3.00 7.5 3.30 7.5 ns clock phase jitter (k, k) tkc var 0.20 0.20 0.20 0.20 ns 4 clock high time (k, k) tkhkl 0.40 0.40 0.40 0.40 cycles clock low time (k, k) tklkh 0.40 0.40 0.40 0.40 ns clock to clock (k, k) tkh kh 1.06 1.13 1.28 1.40 ns dll lock time (k, k) tkc lock 2048 2048 2048 2048 cycles 5 doff low period to dll reset tdofflowtoreset 5 5 5 5 ns output times k, k high to output valid tchqv 0.45 0.45 0.45 0.45 ns k, k high to output hold tchqx -0.45 -0.45 -0.45 -0.45 ns k, k high to echo clock valid tchcqv 0.45 0.45 0.45 0.45 ns k, k high to echo clock hold tchcqx -0.45 -0.45 -0.45 -0.45 ns cq, cq high to output valid tcqhqv 0.20 0.20 0.20 0.20 ns 6 cq, cq high to output hold tcqhqx -0.20 -0.20 -0.20 -0.20 ns 6 k, high to output high-z tchqz 0.45 0.45 0.45 0.45 ns k, high to output low-z tchqx1 -0.45 -0.45 -0.45 -0.45 ns setup times address valid to k rising edge tavkh 0.40 0.40 0.40 0.40 ns control inputs valid to k rising edge tivkh 0.40 0.40 0.40 0.40 ns 2 data-in valid to k, k rising edge tdvkh 0.28 0.28 0.28 0.28 ns hold times ns k rising edge to address hold tkhax 0.40 0.40 0.40 0.40 ns k rising edge to control inputs hold tkhix 0.40 0.40 0.40 0.40 ns k, k rising edge to data-in hold tkhdx 0.28 0.28 0.28 0.28 ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r, w,bw0,bw1 and (bw2, bw3, also for x36) 3. to avoid bus contention, at a given voltage and temperature tchqx1 is bigger than tchqz. the specs as shown do not imply bus contention because tchqx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9v) than tchqz, which is a max parameter (worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 4. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 5. vdd slew rate must be less than 0.1v dc per 50ns for dll lock retention. dll lock time begins once vdd and input clock are stable. 6. echo clock is very tightly controlled to data valid/data hold. by design, there is a ns variation from echo clock to data. the data sheet parameters reflect tester guard bands and test setup variations
18 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams re ad an d deselect cy cl es t imin g di agram t chcqv t chcqx t ch cqx t chcqv t cqhqx t cq hqv t chqz t chqx t chqv t khix t ivkh t khax t avkh t khkh t klkh t khkh t khkl read read nop a1 a2 q1-1 q1-2 q1-3 q1-4 q2-1 nop q2-2 q2-3 q2-4 k k sa r q (data- out) cq cq don?t care undefined note: 1. q1-1 re fers to th e out pu t from ad dres s a1+0, q1-2 , q 1-3, q1 -4 re fers to t he output from add re ss a1+1 , a 1+ 2, a 1+ 3, 2. ou tpu ts are d isabled one cy cl e aft er a nop. which is t he nex internal bu rs t a dd resses fo llowing a 1+0.
integrated silicon solution, inc. 19 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams write and nop timing diagram t khdx t dvkh t khix t khix t ivkh t khax t avkh t khkh t klkh tt khkl t khkh write write nop a1 a2 d1-1 d1-2 d1-3 d1-4 d2-1 d2-2 d2-3 d2-4 nop k k sa w bw x d (data-in) don ? t care undefined b1-1 b1-2 b1-3 b1-4 b2-1 b2-2 b2-3 b2-4 note: (b1-1 refers to all bw x byte controls for d1-1)
20 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams re ad, writ e, and no p timing diagram read write r ead wr ite a1 a2 a3 a4 d2 -1 d2 -2 d2-3 d4-1 d4 -2 d4-3 d4-4 d2 -4 note : if addr ess a3= a2, da ta q 3-1=d2-1, data q 3-2=d2-2, data q 3-3=d 2-3 , and nop q1-1 q1-2 q1-3 q3-1 q3-2 q3-3 q3-4 q1-4 k k sa bw x r w d (dat a-in) d (dat a-o ut) cq cq don?t care u nde fi ned da ta q 3-4=d2-4, t hen wri te data is f orw arded im mediately as r ead res ul ts. nop b2-1 b2-2 b2-3 b2-4 b4-1 b4-2 b4-3 b4-4
integrated silicon solution, inc. 21 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee standard 1149.1, the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. the tap controller has a standard 16-state machine that resets internally on power-up. therefore, a trst signal is not required. signal list tck: test clock tms: test mode select tdi: test data-in tdo: test data-out jtag dc operating characteristics (t a = 0 to + 70 c) operates with jedec standard 8-5 (1.8v) logic signal levels parameter symbol minimum typical maximum units notes jtag input high voltage v ih1 1.3 ? v dd +0.3 v 1 jtag input low voltage v il1 -0.3 ? 0.5 v 1 jtag output high level v oh1 v dd -0.4 ? v dd v1, 2 jtag output low level v ol1 v ss ? 0.4 v 1, 3 1. all jtag inputs and outputs are lvttl-compatible. 2. i oh1 = -2ma 3. i ol1 = +2ma jtag ac test conditions (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%) parameter symbol conditions units input pulse high level v ih1 1.3 v input pulse low level v il1 0.5 v input rise time t r1 1.0 ns input fall time t f1 1.0 ns input and output timing reference level 0.9 v
22 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q jtag ac characteristics (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%) parameter symbol minimum maximum units notes tck cycle time t thth 20 ? ns tck high pulse width t thtl 7 ? ns tck low pulse width t tlth 7 ? ns tms setup t mvth 4 ? ns tms hold t thmx 4 ? ns tdi setup t dvth 4 ? ns tdi hold t thdx 4 ? ns tck low to valid data t tlov ? 7n s1 1. see ac test loading on page 16. jtag timing diagram tck tms tdi tdo t thtl t tlth t thth t thmx t thdx t tlov t mvth t dvth
integrated silicon solution, inc. 23 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q scan register definition register name bit size x18 or x36 instruction 3 bypass 1 id 32 boundary scan 109 id register definition part field bit number and description revision number (31:29) part configuration (28:12) jed ec code (11:1) start bit (0) 4 m x 18 000 000100wx0t0q0b0s0 000 101 001 00 1 2 m x 36 000 000100wx0t0q0b0s0 000 101 001 00 1 part con fi gurati on defi nition : wx = 11 for x36, 10 for x18 t = 1 for dll, 0 for non-dll q = 1 for quadb4 , 0 for ddr -ii b = 1 for burst of 4, 0 for burst of 2 s = 1 for separate i/0, 0 for common i/o
24 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q list of ieee 1149.1 standard violations 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 6.1.1.d instruction set code instruction tdo output notes 000 extest boundary scan register 2,6 001 idcode 32-bit identification register 010 sample-z boundary scan register 1, 2 011 private do not use 5 100 sample boundary scan register 4 101 private do not use 5 110 private do not use 5 111 bypass bypass register 3 1. places qs in high-z in order to sample all input data, regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift-dr state. 4. sample instruction does not place dqs in high-z. 5. t his instruction is reser v ed. i nvok ing this instruction will cause improper sram functional ity. 6. this extest is not ieee 1149.1-compliant. by default, it places q in high-z. if the internal register on the scan chain is se t high, q will be updated with information loaded via a previous sample instruction. the actual transfer occurs during the update ir state after extest is loaded. the value of the internal register can be changed during sample and extest only. jtag block diagram bypass register (1 bit) identification register (32 bits) instruction register (3 bits) tap controller control signals tdi tms tck tdo
integrated silicon solution, inc. 25 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q tap controller state machine test logic reset run test idle select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 01 1 1 0 1 0 0 0 1 1 0 0 0 0 1
26 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams i 3 q boundary scan exit order the same length is used for x18 and x36 i/o configuration. order pin id order pin id order pin id 1 6r 37 10d 73 2c 26 p 3 79 e 7 43 e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 57 n4 19 c7 71 e 67 r4 29 d7 82 f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 99 r 4 59 b 8 11 f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1h 13 9p 49 9a 85 1j 14 10m 50 8b 86 2j 15 11n 51 7c 87 3k 16 9m 52 6c 88 3j 17 9n 53 8a 89 2k 18 11l 54 7a 90 1k 19 11m 55 7b 91 2l 20 9l 56 6b 92 3l 21 10l 57 6a 93 1m 22 11k 58 5b 94 1l 23 10k 59 5a 95 3n 24 9j 60 4a 96 3m 25 9k 61 5c 97 1n 26 10j 62 4b 98 2m 27 11j 63 3a 99 3p 28 11h 64 2a 100 2n 29 10g 65 1a 101 2p 30 9g 66 2b 102 1p 31 11f 67 3b 103 3r 32 11g 68 1c 104 4r 33 9f 69 1b 105 4p 34 10f 70 3d 106 5p 35 11e 71 3c 107 5n 36 10e 72 1d 108 5r 109 internal no te: 1) nc pins as defined on fbga pinouts on page 2 are read as ? don ? t cares ? . 2) state of internal pin (#109) is loaded via jtag
integrated silicon solution, inc. 27 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad p (burst of 4) synchronous srams note : 1. controlling dimension : mm package outline 12/10/2007
28 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) quad (burst of 4) synchronous srams ordering information commercial range: 0c to +70c speed order part no. organization package 400 mhz is61qdpb42m36-400m3 2mx36 165 bga is61qdpb42m36-400m3l 2mx36 165 bga, lead-free is61qdpb44m18-400m3 4mx18 165 bga is61qdpb44m18-400m3l 4mx18 165 bga, lead-free 375 mhz is61qdpb42m36-375m3 2mx36 165 bga is61qdpb42m36-375m3l 2mx36 165 bga, lead-free IS61QDPB44M18-375M3 4mx18 165 bga IS61QDPB44M18-375M3l 4mx18 165 bga, lead-free 333 mhz is61qdpb42m36-333m3 2mx36 165 bga is61qdpb42m36-333m3l 2mx36 165 bga, lead-free is61qdpb44m18-333m3 4mx18 165 bga is61qdpb44m18-333m3l 4mx18 165 bga, lead-free 300 mhz is61qdpb42m36-300m3 2mx36 165 bga is61qdpb42m36-300m3l 2mx36 165 bga, lead-free is61qdpb44m18-300m3 4mx18 165 bga is61qdpb44m18-300m3l 4mx18 165 bga, lead-free

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